Back to projects

System Level Design · Medical Device · Firmware + Hardware

Modular Scintillation Detector

Cost-efficient, modular, multi-channel scintillation detector for automated PET radiopharmaceutical synthesis, firmware, hardware, and 3D-printed enclosure.

Status
January–December 2024 · McGill Capstone · EngerLab (Medical Physics) · Team of 6
Stack
C++ (ESP32 firmware) · ESP-NOW wireless · Altium Designer (PCB) · Autodesk Fusion 360 (enclosure) · LTspice (analog simulation) · Silicon Photomultipliers (SiPM) · 3D printing, soldering, bring-up

Overview

A capstone project at EngerLab to design a cost-efficient, modular, multi-channel scintillation detector for automated PET radiopharmaceutical synthesis. Positron-emission-tomography scans require patients to take radiopharmaceuticals, which must be synthesized and validated using scintillation detectors, and existing detectors are expensive, bulky, and non-modular. Scintillating materials emit photons when exposed to radiation; those photons can be measured and quantized for real-time monitoring.

This was a multi-disciplinary team of six, two Medical Physics PhD students and four engineers (EE/CE/SE). My role: the only firmware developer, the 3D-enclosure designer, and one of two hardware designers, which gave me a large influence on the project’s scope and direction and required constant coordination with the software engineer for firmware–application integration.

What I did

Results

The detector was set up with optical-fiber cables feeding the Signal Acquisition Module input; behind a lead wall sat a scintillating spiral-fiber holder loaded with a low-activity radioactive source. Readings displayed on the application were largely constant, the expected result for a low-activity source.

Honest scope: the team did not fully complete the system (a calibration feature was planned but cut for time, so the result plot is raw data only). The progress made was pivotal to the device’s development and is continuable thanks to extensive documentation.

Approach and key decisions

State machine before code. Two MCUs sampling concurrently and exchanging data over wireless is exactly the kind of system that goes wrong if you start coding before modeling it. Drawing the Leader/Follower state diagrams and the per-transition ESP-NOW message exchange first is what made the concurrency correct.

Build small first. I completed the small RX/TX module before the larger boards, so the communication and packaging layer was proven before the analog-heavy detector module depended on it.

What I’d change. The main PCB’s noise tolerance is the clearest improvement target: separate analog and digital grounds, cluster the analog components, keep digital switching traces away from the sensitive analog path, and impedance-match the high-frequency traces, plus shrink the board.

Figures

The device

Two 3D-printed modular detector units stacked, each with an OLED channel display, power switch, and connectors. Modular detector units: 3D-printed, stackable, one channel each (Fig. 1).

Front view of a detector unit showing the OLED display and controls. Detector front view (Fig. 2).

Back view of a detector unit showing the connectors. Detector back view (Fig. 3).

Firmware

Firmware system: four detector channels, each a Leader (M) and Follower (S) ESP32 pair communicating over ESP-NOW, reporting up to the RX/TX module, which bridges to the host application over UART. Firmware system: each channel is a Leader/Follower ESP32 pair on ESP-NOW; the RX/TX module bridges all channels to the host over UART.

Illustration of sampling and summation during the INTEGRATE state: a signal waveform with discrete sample points marked. Sampling and summation in the INTEGRATE state.

State machines

I modeled both microcontrollers as state machines before writing any firmware.

Follower state machine: IDLE → WAIT → INTEGRATE → TRANSMIT, driven by START, intREQ, and txREQ signals. Follower: samples and integrates from its own ADC, then transmits the sum to the Leader on request.

Leader state machine: IDLE → WAIT → INTEGRATE → RECEIVE → MEAN → TX_RXTX, gated by ACK, START, and NEW signals. Leader: drives the Follower, computes the square-root-product mean of the two sums, and forwards the result to the RX/TX module.

Leader–Follower communication

The Leader and Follower exchange a small set of messages at each state transition over ESP-NOW.

Initialization handshake: Leader sends txInitRequest, Follower replies txInitResponse with ACK, both advance to WAIT. Initialization: the Leader requests, the Follower acknowledges, and both move to WAIT.

Integration handshake: txIntRequest then txIntResponse synchronize the start of an integration window. Integration: the pair synchronizes the start of each integration window.

Transmission: the Leader sends txDataRequest and the Follower replies with txDataPacket carrying its integrated sum. Transmission: the Follower sends its integrated sum to the Leader for the mean computation.

Termination: txStopRequest then txStopResponse return both devices to IDLE. Termination: the Leader stops the channel and both devices return to IDLE.

Data path to the host

Leader–RX/TX packet exchange over ESP-NOW: the Leader sends an RX DATA PACKET (MAC, status, timestamp, mean, packet ID); the RX/TX returns a TX COMMAND PACKET (START, integration period). Leader ↔ RX/TX over ESP-NOW: data packets up, command packets down.

RX/TX to computer table exchange over UART: the RX/TX packs every channel's data into a DATA TABLE for the application and receives a COMMANDS TABLE back. RX/TX ↔ application over UART: a DATA TABLE of all channels up, a COMMANDS TABLE down.

Full firmware system overview combining the per-channel ESP-NOW links, the RX/TX bridge, the host application, and all packet and table structures. Full firmware overview: channels, RX/TX bridge, host, and every packet and table structure together.

Hardware: RX/TX module

CAD renders of the RX/TX module electronics: a microcontroller board and a display board. RX/TX module electronics: microcontroller and display boards (Fig. 9).

Hardware: Signal Acquisition Module (SiPM)

Top of the SiPM PCB showing the SiPM footprint. SiPM PCB, top (Fig. 11).

Bottom of the SiPM PCB showing the bias components and connector. SiPM PCB, bottom: bias resistors, decoupling capacitors, connector (Fig. 11).

Exploded CAD render of the light-tight Signal Acquisition Module enclosure with the SiPM PCB inside. Signal Acquisition Module assembly, light-tight enclosure (Fig. 13).

Hardware: Detector module

LTspice schematic of the analog front end: amplifier circuit and peak-detector circuit built around OPA354 op-amps. LTspice front-end schematic: amplifier and peak-detector stages, simulated before layout (Fig. 14).

LTspice transient waveforms of the signal, gate, and peak-detector nodes. Simulated transient response of the signal (V_sig), gate (V_g), and peak (V_p) nodes (Fig. 14).

Annotated CAD render of the main detector PCB labeling the dual amplifier and peak-detector circuits, microcontrollers, DC-DC booster, SiPM interface, coax outputs, and test points. Main detector PCB, annotated: dual analog front ends, two microcontrollers, DC-DC booster, SiPM interface, coax outputs (Fig. 15).

Exploded CAD render of the detector module showing the main PCB inside the enclosure with SiPM modules and front panel. Detector module, exploded view (Fig. 16).

Assembled detector module enclosure with coax outputs and power input. Detector module, assembled (Fig. 16).

Modularity and results

CAD render of stacked detector modules joined by vertical power connectors. Modularity: units stack and share power through vertical connectors from one adapter (Fig. 17).

Bench experiment setup on an optical table with the detector behind a lead wall. Experiment setup: optical-fiber input, lead wall, low-activity source (Fig. 18).

CAD render of the spiral optical-fiber holder for the scintillating material. Spiral fiber holder for the scintillating material (Fig. 19).

Plot of mean measured channel value over time, showing a largely constant raw signal. Measured raw data: mean channel value over time, largely constant for the low-activity source (Fig. 20).